(a) Field of the Invention
The invention relates to an apparatus and a method for testing a high-speed semiconductor device.
(b) Description of the Prior Art
Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is a memory technique developed based upon SDRAM. Unlike SDRAM that is capable of only supporting one data operation during each clock period, DDR SDRAM has capability of executing two data operations during each clock period. Therefore, not only bandwidth of memory is doubled but also data transmission capacity is multiplied. For the aforesaid advantage, DDR SDRAM is extensively applied in computer system platforms including personal computers, workstations, servers, laptop computers, portable devices, computer networks, and communication products, and consequently stands as a mainstream product in memory techniques. Along with technique advancement, data rate of DDR SDRAM has increased from 200/266 MHz to 533/667 MHz, and can promisingly be further increased to 800 MHz/1.066 GHz. It is to be noted that frequency upgrading is also an arduous challenge for testing techniques.
Referring to FIG. 1 showing a test system 1 applied in DDR SDRAM, the test system 1 comprises a tester 10 that may be an Advantest 5592/5593 tester manufactured by Advantest Corporation and is mainly for generating test patterns. The tester 10 is divided into several stations, and has two stations 12 and 14 supposed an Advantest 5592/5593 tester is adopted. The stations 12 and 14 are connected to respective test fixtures 16 and 18 as shown in FIG. 1.
Referring to FIG. 2 showing a schematic view of the test fixture 16, the test fixture 16 has a test head 20, a common motherboard 22 and a socket board 24. The test head 20 is devised with elements including a driver and a comparator therein for driving and comparing signals. The common motherboard 22 has a coaxial cable therein for connecting the common motherboard 22 to the socket board 24. The socket board 24 has a socket board printed circuit board (PCB) and a socket connector for fastening an integrated circuit (IC). The device-under-test (DUT) is inserted to the socket board 24. To simplify illustrations, only two DUTs 26A and 26B are shown in FIG. 2. In practical, supposed an Advantest 5592/5593 tester is used, a number of DUTs may be 64 or even 128. For that FIG. 2 serves for illustration purposes only, the test head 20 is electrically coupled to the common motherboard 22, and the common motherboard 22 is electrically coupled to the socket board 24.
Pins of each of the DUTs 26A and 26B are generally divided into input pins and input/output (I/O) pins. Referring to FIG. 3 showing a circuit schematic diagram of a conventional test apparatus 3 applied to an input pin. The conventional test apparatus 3 applied to an input pin is disposed in the test fixture 16 shown in FIG. 2. The test apparatus 3 comprises a driver 30 connected to one input end of the DUT 26A through a pin 32A whereas another pin 32B is connected to one input end of the DUT 26B. In other words, the DUTs 26A and 26B are both driven and controlled by the driver 30.
It is to be noted that I/O end of DDR SDRAM are differentiated in 4-bit, 8-bit and 16-bit. Connection configuration in FIG. 3 is suitable for testing 4-bit I/O and 8-bit I/O DDR SDRAM but not 16-bit I/O DDR SDRAM. For 16-bit applications, it is necessary that the pin 32B be left floating as shown in FIG. 4. To be more precise, the driver 30 is merely capable of corresponding to one DUT 26A. At this point, impedance of the floating pin 32B is rather great that apparent reflection of signals transmitted by the driver 30 is produced to affect accuracy of test results. Reflection becomes even more severe as signal frequencies get greater.
Referring to FIG. 5 showing a circuit schematic diagram of a prior test apparatus 5 applied to an I/O end. The prior test apparatus 5 applied to an I/O end is disposed in the test fixture 16 in FIG. 2. The test apparatus 5 comprises a driver 50, a switch 51, a resistor 52, a voltage terminal 53, a comparator 54, a switch 55, a resistor 56 and a voltage terminal 57. An input of the driver 50 is for receiving a test pattern PAT, and an output end thereof is connected to the DUT 26A via an I/O pin 59A. In other words, the driver 50 is for merely corresponding to one DUT 26A. The switch 51, the resistor 52 and the voltage terminal 53 are connected in series between a driver enable signal (/DRE) and ground. The comparator 54 is connected to the I/O pin 59A. When data are read from the I/O pin 59A, the comparator 54 determines whether the data are at logic high or logic low. The switch 55, the resistor 56 and the voltage terminal 57 are connected in series between the comparator 54 and ground. Under a write mode, the switches 51 and 55 are turned off through control of an OUTL signal, and the enable signal /DRE is at logic low for enabling the driver 50, such that the output end of the driver outputs the test pattern signal PAT, with the enable signal /DRE simultaneously disabling the switch 58. Under a read mode, the switches 51 and 55 are turned on through control of an OUTL signal, and the enable signal /DRE is at logic high for disabling the driver 50 and enabling the switch 58, such that the resistor 52 and the voltage terminal 53 are coupled to the I/O pin 59A. The read data whether being logic high or logic low is determined by the comparator 54. Likewise, the test apparatus applied to the DUT 26B operates in an identical or similar method as that disclosed in FIG. 5. To be more accurate, the DUTs 26A and 26B cannot share a same driver. There are test fixtures especially tailored for 16-bit DDR SDRAM, and these test fixtures are often purchased by users commonly being memory manufacturers or test houses. However, a complete set of test fixtures is considered quite resource uneconomical for that each costs at least millions of dollars.